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SH7261 Datasheet(PDF) 166 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 166 Page - Renesas Technology Corp

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Section 6 Interrupt Controller (INTC)
Rev. 2.00 Sep. 07, 2007 Page 134 of 1312
REJ09B0320-0200
6.3.11
DMA Transfer Request Enable Register 1 (DREQER1)
DMA transfer request enable register 1 (DREQER1) is an 8-bit readable/writable register that
enables/disables the SCIF (channels 0 to 3) DMA transfer requests, and enables/disables CPU
interrupt requests.
DMA transfer request enable register 1 is initialized by a power-on reset or in deep standby mode.
0
1
2
3
4
5
6
7
00
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCIF
3ch TX
SCIF
3ch RX
SCIF
2ch TX
SCIF
2ch RX
SCIF
1ch TX
SCIF
1ch RX
SCIF
0ch TX
SCIF
0ch RX
Bit:
Initial value:
R/W:
Bit
Bit Name
Initial
Value
R/W
Description
7
SCIF 3ch TX
0
R/W
6
SCIF 3ch RX
0
R/W
5
SCIF 2ch TX
0
R/W
4
SCIF 2ch RX
0
R/W
3
SCIF 1ch TX
0
R/W
2
SCIF 1ch RX
0
R/W
1
SCIF 0ch TX
0
R/W
0
SCIF 0ch RX
0
R/W
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
request enabled
1: DMA transfer request enabled, CPU interrupt request
disabled



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