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SH7261 Datasheet(PDF) 162 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 162 Page - Renesas Technology Corp |
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162 / 1348 page  Section 6 Interrupt Controller (INTC) Rev. 2.00 Sep. 07, 2007 Page 130 of 1312 REJ09B0320-0200 6.3.7 PINT Interrupt Request Register (PIRR) PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to PINT0. PIRR is initialized by a power-on reset or in deep standby mode. 0 1 2 3 4 5 6 7 — — — — — — — — 00 0 0 0 0 0 0 00 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit: Initial value: R/W: 15 14 13 12 11 10 9 8 PINT 7R PINT 6R PINT 5R PINT 4R PINT 3R PINT 2R PINT 1R PINT 0R Bit Bit Name Initial Value R/W Description 15 to 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 PINT7R 0 R 6 PINT6R 0 R 5 PINT5R 0 R 4 PINT4R 0 R 3 PINT3R 0 R 2 PINT2R 0 R 1 PINT1R 0 R 0 PINT0R 0 R PINT Interrupt Request These bits indicate the status of the PINT7 to PINT0 interrupt requests. 0: No interrupt request at PINTn pin 1: Interrupt request at PINTn pin [Legend] n = 7 to 0 |
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