SH7261 datasheet(159/1348 Pages) RENESAS

159 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 127 of 1312

REJ09B0320-0200

6.3.4

Interrupt Control Register 2 (ICR2)

ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7

to PINT0 individually: low level or high level. ICR2 is initialized by a power-on reset or in deep

standby mode.

Bit:

Initial value:

R/W:

9876543210

R/W

RRRRRRRR

—————

—

PINT

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

PINT7S

R/W

PINT6S

R/W

PINT5S

R/W

PINT4S

R/W

PINT3S

R/W

PINT2S

R/W

PINT1S

R/W

PINT0S

R/W

PINT Sense Select

These bits select whether interrupt signals

corresponding to pins PINT7 to PINT0 are detected by

a low level or high level.

0: Interrupt request is detected on low level of PINTn

input

1: Interrupt request is detected on high level of PINTn

input

[Legend]

n = 7 to 0

6.3.5

IRQ Interrupt Request Register (IRQRR)

IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0.

If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after

reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.

IRQRR is initialized by a power-on reset or in deep standby mode.

SH7261 Datasheet(PDF) 159 Page - Renesas Technology Corp

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