SH7261 datasheet(160/1348 Pages) RENESAS

160 / 1348 page

Section 6 Interrupt Controller (INTC)

Rev. 2.00 Sep. 07, 2007 Page 128 of 1312

REJ09B0320-0200

Bit:

Initial value:

R/W:

987654321

00000000

R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note:

Only 0 can be written to clear the flag after 1 is read.

00000000

RRRRRRRR

————————

IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

IRQ7F

R/(W)*

IRQ6F

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

IRQ0F

R/(W)*

IRQ Interrupt Request

These bits indicate the status of the IRQ7 to IRQ0

interrupt requests.

Level detection:

0: IRQn interrupt request has not occurred

[Clearing condition]

• IRQn input is high

1: IRQn interrupt has occurred

[Setting condition]

• IRQn input is low

Edge detection:

0: IRQn interrupt request is not detected

[Clearing conditions]

• Cleared by reading IRQnF while IRQnF = 1, then

writing 0 to IRQnF

• Cleared by executing IRQn interrupt exception

handling

1: IRQn interrupt request is detected

[Setting condition]

• Edge corresponding to IRQn1S or IRQn0S of

ICR1 has occurred at IRQn pin

[Legend]

n = 7 to 0

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