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SH7261 Datasheet(PDF) 163 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 163 Page - Renesas Technology Corp

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Section 6 Interrupt Controller (INTC)
Rev. 2.00 Sep. 07, 2007 Page 131 of 1312
REJ09B0320-0200
6.3.8
Bank Control Register (IBCR)
IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority
level. IBCR is initialized to H'0000 by a power-on reset or in deep standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9876543210
0000000000000000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
—
Bit
Bit Name
Initial
Value
R/W
Description
15
E15
0
R/W
14
E14
0
R/W
13
E13
0
R/W
12
E12
0
R/W
11
E11
0
R/W
10
E10
0
R/W
9
E9
0
R/W
8
E8
0
R/W
7
E7
0
R/W
6
E6
0
R/W
5
E5
0
R/W
4
E4
0
R/W
3
E3
0
R/W
2
E2
0
R/W
1
E1
0
R/W
Enable
These bits enable or disable use of register banks for
interrupt priority levels 15 to 1. However, use of register
banks is always disabled for the user break interrupts.
0: Use of register banks is disabled
1: Use of register banks is enabled
0
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.



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