SH7261 datasheet(229/1348 Pages) RENESAS

229 / 1348 page

Section 8 Cache

Rev. 2.00 Sep. 07, 2007 Page 197 of 1312

REJ09B0320-0200

8.3.2

Read Access

(1)

Read Hit

In a read access, data is transferred from the cache to the CPU. LRU is updated so that the hit way

is the latest.

(2)

Read Miss

An external bus cycle starts and the entry is updated. The way replaced follows table 8.4. Entries

are updated in 16-byte units. When the desired data that caused the miss is loaded from external

memory to the cache, the data is transferred to the CPU in parallel with being loaded to the cache.

When it is loaded in the cache, the V bit is set to 1, and LRU is updated so that the replaced way

becomes the latest. In operand cache, the U bit is additionally cleared to 0. When the U bit of the

entry to be replaced by updating the entry in write-back mode is 1, the cache update cycle starts

after the entry is transferred to the write-back buffer. After the cache completes its update cycle,

the write-back buffer writes the entry back to the memory. The write-back unit is 16 bytes.

8.3.3

Prefetch Operation (Only for Operand Cache)

(1)

Prefetch Hit

LRU is updated so that the hit way becomes the latest. The contents in other caches are not

modified. No data is transferred to the CPU.

(2)

Prefetch Miss

No data is transferred to the CPU. The way to be replaced follows table 8.3. Other operations are

the same in case of read miss.

8.3.4

Write Operation (Only for Operand Cache)

(1)

Write Hit

In a write access in write-back mode, the data is written to the cache and no external memory

write cycle is issued. The U bit of the entry written is set to 1 and LRU is updated so that the hit

way becomes the latest.

In write-through mode, the data is written to the cache and an external memory write cycle is

issued. The U bit of the written entry is not updated and LRU is updated so that the replaced way

becomes the latest.

SH7261 Datasheet(PDF) 229 Page - Renesas Technology Corp