SH7261 datasheet(232/1348 Pages) RENESAS

232 / 1348 page

Section 8 Cache

Rev. 2.00 Sep. 07, 2007 Page 200 of 1312

REJ09B0320-0200

8.3.6

Coherency of Cache and External Memory

Use software to ensure coherency between the cache and the external memory. When memory

shared by this LSI and another device is mapped in the address space to be cached, operate the

memory-mapped cache to invalidate and write back as required.

8.4

Memory-Mapped Cache

To allow software management of the cache, cache contents can be read and written by means of

MOV instructions. The instruction cache address array is mapped onto addresses H'F0000000 to

H'F07FFFFF, and the data array onto addresses H'F1000000 to H'F17FFFFF. The operand cache

address array is mapped onto addresses H'F0800000 to H'F0FFFFFF, and the data array onto

addresses H'F1800000 to H'F1FFFFFF. Only longword can be used as the access size for the

address array and data array, and instruction fetches cannot be performed.

8.4.1

Address Array

To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field

(for write accesses) must be specified.

In the address field, specify the entry address selecting the entry, the W bit for selecting the way,

and the A bit for specifying the existence of associative operation. In the W bit, B'00 is way 0,

B'01 is way 1, B'10 is way 2, and B'11 is way 3. Since the access size of the address array is fixed

at longword, specify B'00 for bits 1 and 0 of the address.

The tag address, LRU bits, U bit (only for operand cache), and V bit are specified as data. Always

specify 0 for the upper three bits (bits 31 to 29) of the tag address.

For the address and data formats, see figure 8.4.

The following three operations are possible for the address array.

(1)

Address Array Read

The tag address, LRU bits, U bit (only for operand cache), and V bit are read from the entry

address specified by the address and the entry corresponding to the way. For the read operation,

associative operation is not performed regardless of whether the associative bit (A bit) specified by

the address is 1 or 0.

SH7261 Datasheet(PDF) 232 Page - Renesas Technology Corp