SH7261 datasheet(231/1348 Pages) RENESAS

231 / 1348 page

Section 8 Cache

Rev. 2.00 Sep. 07, 2007 Page 199 of 1312

REJ09B0320-0200

Table 8.8

Cache Operations

Cache

CPU Cycle

Hit/

miss

Write-back mode/

write through mode

U Bit

External Memory

Accession

(through internal bus)

Cache Contents

Hit



Not generated

Not renewed

Instruction

cache

Instruction

fetch

Miss



Cache renewal cycle is

generated.

Renewed to new values by

cache renewal cycle

Operand

cache

Prefetch/

read

Hit

Either mode is available x

Not generated

Not renewed

Miss

Write-through mode



Cache renewal cycle is

generated.

Renewed to new values by

cache renewal cycle

Write-back mode

Cache renewal cycle is

generated

Renewed to new values by

cache renewal cycle

Cache renewal cycle is

generated. Succeedingly

write-back cycle in write-

back buffer is generated

Renewed to new values by

cache renewal cycle

Write

Hit

Write-through mode



Write cycle CPU issues is

generated.

Renewed to new values by

write cycle the CPU issues

Write-back mode

Not generated

Renewed to new values by

write cycle the CPU issues

Miss

Write-through mode



Write cycle CPU issues is

generated.

Not renewed*

Write-back mode

Cache renewal cycle is

generated.

Renewed to new values by

cache renewal cycle.

Subsequently renewed

again to new values in

write cycle CPU issues.

Cache renewal cycle is

generated. Succeedingly

write-back cycle in write-

back buffer is generated

Renewed to new values by

cache renewal cycle.

Subsequently renewed

again to new values in

write cycle CPU issues.

[Legend]

Don't care

Note:

Cache renewal cycle: 16-byte read access, write-back cycle in write-back buffer: 16-byte

write access

Neither LRU renewed. LRU is renewed in all other cases.

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