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SH7261 Datasheet(PDF) 234 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 234 Page - Renesas Technology Corp

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Section 8 Cache
Rev. 2.00 Sep. 07, 2007 Page 202 of 1312
REJ09B0320-0200
(1)
Data Array Read
The data specified by the L bit in the address is read from the entry address specified by the
address and the entry corresponding to the way.
(2)
Data Array Write
The longword data specified by the data is written to the position specified by the L bit in the
address from the entry address specified by the address and the entry corresponding to the way.
31
23 22
13 12 11
31
29 28
10
43210
111100000
111100000
111100010
*----------*
*----------*
*----------*
*----------*
*----------*
*----------*
W
*
LRU
X
X
000
X
V
E
00
0
31
23 22
13 12 11 10
4
3
2
1
0
31
0
W
0
L
0
31
23 22
13 12 11 10
11 10 9
43210
43210
W
*
A0
0
31
23 22
13 12 11
31
29 28
10
43210
111100001
111100001
111100011
W
*
LRU
X
X
000
U
V
E
00
0
31
23 22
13 12 11 10
4
3
2
1
0
31
0
W
0
L
0
31
23 22
13 12 11 10
11 10 9
43210
43210
W
*
A0
0
1. Instruction cache
1.1 Address array access
(a) Address specification
Read access
Write access
(b) Data specification (both read and write accesses)
1.2 Data array access (both read and write accesses)
(a) Address specification
Tag address (28 to 11)
Entry address
(b) Data specification
Longword data
*:
Don't care
E:
Bit 10 of entry address for read, don't care for write
X:
0 for read, don't care for write
[Legend]
Entry address
Tag address (28 to 11)
Entry address
Entry address
Entry address
Entry address
Longword data
2.2 Data array access (both read and write accesses)
(a) Address specification
(b) Data specification
2. Operand cache
2.1 Address array access
(a) Address specification
Read access
Write access
(b) Data specification (both read and write accesses)
Figure 8.4 Specifying Address and Data for Memory-Mapped Cache Access



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