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SH7261 Datasheet(PDF) 238 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 238 Page - Renesas Technology Corp |
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238 / 1348 page ![]() Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 206 of 1312 REJ09B0320-0200 Area controller (CSC) Access controller SDRAM controller (SDRAMC) CS6 to CS0 RD WR3 to WR0 WAIT A27 to A0 BC3 to BC0 D31 to D0 SDCS1, SDCS0 SDRAS, SDCAS SDWE, SDCKE DQM3 to DQM0 CSMODn CS1WCNTn CS2WCNTn SDRFCNT0/1 SDIR0/1 SDmADR SDmTR SDmMOD [Legend] Note: n = 0 to 6, m = 0 and 1 CSMODn: CSn mode register CS1WCNTn: CSn wait control register 1 CS2WCNTn: CSn wait control register 2 CSnCNT: CSn control register CSnREC: CSn recovery cycle setting register SDCmCNT: SDRAMCm control register SDRFCNT0/1: SDRAM refresh control register 0/1 SDIR0/1: SDRAM initialization register 0/1 SDmADR: SDRAMm address register SDmTR: SDRAMm timing register SDmMOD: SDRAMm mode register SDPWDCNT: SDRAM power-down control register SDDPWDCNT: SDRAM deep-power-down control register SDSTR: SDRAM status register SDCKSCNT: SDRAM clock stop control signal setting register SDPWDCNT SDDPWDCNT SDSTR SDCKSCNT CSnCNT CSnREC SDCmCNT Figure 9.1 Block Diagram of BSC |
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