SH7261 datasheet(241/1348 Pages) RENESAS

241 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 209 of 1312

REJ09B0320-0200

9.3

Area Overview

9.3.1

Address Map

In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled, cache-

disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved areas)

according to the upper bits of the address.

External address spaces CS5 to CS0 are cache-enabled when internal address A29 = 0 and cache-

disabled when A29 = 1. The CS6 space is always cache-disabled.

The kind of memory to be connected and the data bus width are specified independently for each

partial space. The address map for the external address space is listed below.

Table 9.2

Address Map

Internal Address

Space

Memory to be Connected

Cache

H'00000000 to H'03FFFFFF

CS0

Normal space

H'04000000 to H'07FFFFFF

CS1

Normal space

H'08000000 to H'0BFFFFFF

SDRAM0

SDRAM

H'0C000000 to H'0FFFFFFF

SDRAM1

SDRAM

H'10000000 to H'13FFFFFF

CS2

Normal space

H'14000000 to H'17FFFFFF

CS3

Normal space

H'18000000 to H'1BFFFFFF

CS4

Normal space

H'1C000000 to H'1FFFFFFF

CS5

Normal space

Cache-

enabled

H'20000000 to H'23FFFFFF

CS0

Normal space

H'24000000 to H'27FFFFFF

CS1

Normal space

H'28000000 to H'2BFFFFFF

SDRAM0

SDRAM

H'2C000000 to H'2FFFFFFF

SDRAM1

SDRAM

H'30000000 to H'33FFFFFF

CS2

Normal space

H'34000000 to H'37FFFFFF

CS3

Normal space

H'38000000 to H'3BFFFFFF

CS4

Normal space

H'3C000000 to H'3FFFFFFF

CS5

Normal space

Cache-

disabled

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