SH7261 datasheet(245/1348 Pages) RENESAS

245 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 213 of 1312

REJ09B0320-0200

Abbreviation

R/W

Initial Value

Address

Access

Size

SDRAM power-down control

SDPWDCNT

R/W

H'00000000

H'FF422010

8, 16, 32

SDRAM deep-power-down

control register

SDDPWDCNT R/W

H'00000000

H'FF422014

8, 16, 32

SDRAM0 address register

SD0ADR

R/W

H'00000x0x

H'FF422020

8, 16, 32

SDRAM0 timing register

SD0TR

R/W

H'000xxx0x

H'FF422024

8, 16, 32

SDRAM0 mode register

SD0MOD

R/W

H'0000xxxx

H'FF422028

16, 32

SDRAM1 address register

SD1ADR

R/W

H'00000x0x

H'FF422040

8, 16, 32

SDRAM1 timing register

SD1TR

R/W

H'000xxx0x

H'FF422044

8, 16, 32

SDRAM1 mode register

SD1MOD

R/W

H'0000xxxx

H'FF422048

16, 32

SDRAM status register

SDSTR

R/W

H'00000000

H'FF4220E4

8, 16, 32

SDRAM clock stop control

signal setting register

SDCKSCNT

R/W

H'0000000F

H'FF4220E8

8, 16, 32

AC characteristics switching

ACSWR

R/W

H'00000000

H'FFFD8808

8, 16, 32

Note:

Depends on the setting of the MD pin.

9.4.1

CSn Control Register (CSnCNT) (n = 0 to 6)

CSnCNT selects the width of the external bus and controls the operation of the CSC interface.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

R/W

0000000000000000

RRRRRRRRRRRRRRRR

—

BSIZE[1:0]

EXENB

—

——

—

———————

Bit

Bit Name

Initial

Value

R/W

Description

31 to 22



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

SH7261 Datasheet(PDF) 245 Page - Renesas Technology Corp

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