SH7261 datasheet(247/1348 Pages) RENESAS

247 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 215 of 1312

REJ09B0320-0200

9.4.2

CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6)

CSnREC specifies the number of data recovery cycles to be inserted after read or write accesses.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

R/W

0000000000000000

RRRRRRRRRRRRRRRR

—

WRCV[3:0]

RRCV[3:0]

—

————

—————————————

Bit

Bit Name

Initial

Value

R/W

Description

31 to 28



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

27 to 24 WRCV[3:0]

0000

R/W

Post-Write Data Recovery Cycle Setting

These bits specify the number of data recovery cycles

to be inserted after write accesses to the external bus.

If a value other than 0 is selected, between 1 and 15

data recovery cycles are inserted when a write access

to the external bus is followed by a read access to the

external bus. (Data recovery cycles are inserted even

when access is performed sequentially to the same

CSC channel.) Note that if idle cycles occur between

accesses to the external bus, the number of data

recovery cycles inserted is reduced by the number of

idle cycles.

0000: 0 cycle

0001: 1 cycles

1111: 15 cycles

23 to 20



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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