SH7261 datasheet(249/1348 Pages) RENESAS

249 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 217 of 1312

REJ09B0320-0200

9.4.3

SDRAMCm Control Register (SDCmCNT) (m = 0, 1)

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

R/W

0000000000000000

RRRRRRRRRRRRRRRR

—

BSIZE[1:0]

EXENB

—

———

—

——

Bit

Bit Name

Initial

Value

R/W

Description

31 to 22



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

21, 20

BSIZE[1:0]

R/W

External Bus Width Select

These bits specify the width of the data bus for the

external device of the corresponding channel of CSC.

10: 8-bit bus

00: 16-bit bus

01: 32-bit bus

19 to 17



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

EXENB

R/W

Operation Enable

This bit enables or disables the operation for the

corresponding channel of CSC.

0: Operation disabled

1: Operation enabled

15 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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