SH7261 datasheet(253/1348 Pages) RENESAS

253 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 221 of 1312

REJ09B0320-0200

9.4.5

CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6)

CS1WCNTn specifies the number of wait states inserted into the read/write cycle or page

read/page write cycle.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0001111100011111

R/W

0000011100000111

RRRRR

R/W

RRRRR

R/W

—

CSRWAIT[4:0]

—

CSWWAIT[4:0]

—

CSPRWAIT[2:0]

—

CSPWWAIT[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 29



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

28 to 24 CSRWAIT

[4:0]

11111

R/W

Read Cycle Wait Select

These bits specify the number of wait states inserted

into the initial normal read cycle and page read cycle.

00000: 0 wait states

11111: 31 wait states

23 to 21



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

20 to 16 CSWWAIT

[4:0]

11111

R/W

Write Cycle Wait Select

These bits specify the number of wait states inserted

into the initial normal write cycle and page write cycle.

00000: 0 wait states

11111: 31 wait states

15 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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