SH7261 datasheet(255/1348 Pages) RENESAS

255 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 223 of 1312

REJ09B0320-0200

9.4.6

CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6)

CS2WCNTn specifies the number of wait states and the number of delay cycles.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

R/W

0000000000000111

R/W

—

CSON[2:0]

—

WDON[2:0]

—

WRON[2:0]

—

RDON[2:0]

—

WDOFF[2:0]

—

CSWOFF[2:0]

—

CSROFF[2:0]

Bit

Bit Name

Initial

Value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

30 to 28 CSON

[2:0]

000

R/W

CS Assert Wait Select

These bits specify the number of wait states inserted

before the external chip select signal (

CSn) is asserted.

000: 0 wait state

111: 7 wait states



Reserved

This bit is always read as 0. The write value should

always be 0.

26 to 24 WDON

[2:0]

000

R/W

Write Data Output Wait Select

These bits specify the number of wait states inserted

before data is output to the external data bus.

000: 0 wait state

111: 7 wait states



Reserved

This bit is always read as 0. The write value should

always be 0.

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