SH7261 datasheet(259/1348 Pages) RENESAS

259 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 227 of 1312

REJ09B0320-0200

9.4.8

SDRAM Refresh Control Register 1 (SDRFCNT1)

SDRFCNT1 controls auto-refresh operation.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRR

R/W

———————————————

—

DRFEN

DREFW[3:0]

DRFC[11:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 17



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DRFEN

R/W

Auto-Refresh Operation Enable

This bit controls auto-refresh operation for all channels

simultaneously. When DRFEN is cleared to 0, auto-

refresh operation does not take place. Auto-refresh

operates when DRFEN is set to 1. Clearing this bit to 0

while auto-refresh is enabled causes DRFEN to be

cleared to 0, and auto-refresh operation to halt, after

the end of the next auto-refresh cycle. Setting this bit to

1 while auto-refresh is enabled causes auto-refresh

operation to commence as soon as DRFEN is set to 1,

and refresh requests are then generated at fixed

intervals determined by a counter. The interval at which

refresh requests are generated is determined by the

set value of the auto-refresh request interval setting

(DRFC) bits. Refresh requests are not accepted while

SDRAM is being accessed; they must wait until the

access completes. If a SDRAM access and refresh

request are generated at the same time, the refresh

request takes precedence.

0: Auto-refresh disabled

1: Auto-refresh enabled

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