SH7261 datasheet(261/1348 Pages) RENESAS

261 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 229 of 1312

REJ09B0320-0200

Auto-Refresh Request Interval and DRFC Set Value:

SDRAMC includes a 12-bit refresh counter that generates auto-refresh requests at fixed intervals.

The following equation is used to calculate the set value for the DRFC bits from the auto-refresh

request interval.

DRFC = (Auto-refresh request interval / System clock cycle) – 1

Auto-refresh requests are not accepted while SDRAM is being accessed; they must wait until the

access completes. However, the counter value is updated regardless or whether or not the request

was accepted. Note that if two or more auto-refresh requests are generated while SDRAM is being

accessed, the second and subsequent requests are ignored.

9.4.9

SDRAM Initialization Register 0 (SDIR0)

SDIR0 specifies the SDRAM initialization sequence timing.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

00000

R/W

—

————————————

———————————

—

DPC[2:0]

DARFC[3:0]

DARFI[3:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 11



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

10 to 8

DPC[2:0]

Undefined

R/W

Initialization Precharge Cycle Count Setting

These bits specify the number of precharge cycles in

the SDRAM initialization sequence.

000: 3 cycles

001: 4 cycles

111: 10 cycles

SH7261 Datasheet(PDF) 261 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 261 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL