SH7261 datasheet(263/1348 Pages) RENESAS

263 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 231 of 1312

REJ09B0320-0200

9.4.10

SDRAM Initialization Register 1 (SDIR1)

SDIR1 controls activation of the SDRAM initialization sequence.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRR

R/W

0000000000000000

RRRRRRRRRRRRRRR

R/W

—

DIN

IST

—

DIN

IRQ

Bit

Bit Name

Initial

Value

R/W

Description

31 to 17



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DINIST

R/W

Initialization Status

When set to 1, this bit indicates that an SDRAM

initialization sequence is in progress for channel

SDRAM0 or SDRAM1.

0: Initialization sequence not progress

1: Initialization sequence in progress

15 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DINIRQ

R/W

Common Initialization Sequence Start

Setting this bit to 1 causes the SDRAM initialization

sequence to start and automatically sets the

initialization status bit (DINIST) to 1. The initialization

status bit (DINIST) is cleared automatically after the

initialization sequence ends. The value written to the

DINIRQ bit is not retained.

0: Invalid

1: Initialization sequence start

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