SH7261 datasheet(266/1348 Pages) RENESAS

266 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 234 of 1312

REJ09B0320-0200

9.4.13

SDRAMm Address Register (SDmADR) (m = 0, 1)

SDmADR specifies the data bus width and the channel size of SDRAM.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

000000

—

00000

—

RRRRRR

R/W

RRRRR

R/W

—

——————

————

—

————

DDBW[1:0]

DSZ[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 10



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

9, 8

DDBW[1:0] Undefined

R/W

SDRAM Data Bit Width Setting

These bits specify the width of the SDRAM bus.

00: 8 bits

01: 16 bits

10: 32 bits

11: Setting prohibited

7 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

2 to 0

DSZ[2:0]

Undefined

R/W

Channel Size Setting

These bits specify the size of channels 0 and 1. If a

size smaller than SDRAM area 0 or 1 is selected, ghost

memory will result. When accessing 32-bit data in

SDRAM with a 16-bit bus width, the 16 bits of the first

half of the address (A1 = 0) are accessed first, and

then the 16 bits of the second half of the address (A1 =

1) are accessed.

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