SH7261 datasheet(269/1348 Pages) RENESAS

269 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 237 of 1312

REJ09B0320-0200

9.4.15

SDRAMm Mode Register (SDmMOD) (m = 0, 1)

SDmMOD specifies the values to be written to the SDRAM mode register or extended mode

command to be issued automatically to SDRAM.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

R/W

————————————————

———————————————

—

DMR[14:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 15



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

14 to 0

DMR[14:0] Undefined

R/W

Mode Register Setting

Writing to these bits causes a mode register set

command or extended mode register set command to

be issued to SDRAM. The setting of the DMR bits is

output as A16 to A2 signals. The distinction between

the mode register set command and extended mode

SDRAM bank address.

Write operation: A mode register set command is

issued.

DMR bit

b14

b13

...

↓

A16 to A2 signal

A16

A15

...

Notes: The following points should be kept in mind regarding SDRAMm mode register settings.

1. Make sure to set a burst length of 1 for SDRAM. Operation cannot be guaranteed with

settings other than burst length 1.

2. The SDRAM column latency must match the setting of the SDRAM controller column

latency setting bits (DCL) in SDRAMC. Operation cannot be guaranteed if the latency

settings do not agree.

3. Check to make sure the status bits (DSRFST, DPWDST, DDPDST, and DMRSST) in

the SDRAM status register (SDSTR) are all cleared to 0.

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