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SH7261 Datasheet(PDF) 273 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 273 Page - Renesas Technology Corp |
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273 / 1348 page  Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 241 of 1312 REJ09B0320-0200 Bit Bit Name Initial Value R/W Description 7 to 0 DCKSC [7:0] H'0F R/W Clock Stop Control Signal Assert Cycle Count Setting These bits specify the interval from the point at which the deep-power-down transition command is issued until the clock stop signal goes high level to stop the CKIO (high level), and the interval from the point at which the clock stop signal goes low level to start the CKIO operation until the recover command is issued. 00000000: 0 cycle : 00001111: 15 cycles : 11111111: 255 cycles 9.4.18 AC Characteristics Switching Register (ACSWR) When writing to the external address space or making SDRAM settings in power-on reset exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in ACSWR to B'0011 beforehand. ACSWR is initialized to H'00000000 by a power-on reset and entry to deep standby mode, but is not initialized by a manual reset, entry to sleep mode, or entry to software standby mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit: Initial value: R/W: 15 14 13 12 11 10 9876543210 Bit: Initial value: R/W: 0000000000000000 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000000000000000 — — — — — — ———— ———— ————— — — — — — — — — — ACOSW[3:0] Bit Bit Name Initial Value R/W Description 31 to 4 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. |
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