SH7261 datasheet(271/1348 Pages) RENESAS

271 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 239 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

DPWDST

Power-Down Transition/Recovery Status

When set to 1, this bit indicates that a transition to or

recovery from power-down mode is in progress for a

channel from SDRAM0 to SDRAM3.

0: Initialization sequence not in progress

1: Initialization sequence in progress

DDPDST

Deep-Power-Down Transition/Recovery Status

When set to 1, this bit indicates that a transition to or

recovery from deep-power-down mode is in progress

for channel SDRAM0 or SDRAM1.

0: Transition/recovery not in progress

1: Transition/recovery in progress

DMRSST

Mode Register Setting Status

When set to 1, this bit indicates that mode register

setting is in progress for channel SDRAM0 or

SDRAM1.

0: Mode register setting not in progress

1: Mode register setting in progress

"Transition to or recovery from in progress" refers to the interval from the point at which the bits

listed in table 9.5 are written to until the corresponding commands are issued.

Table 9.5

List of Status Registers and Bits Requiring Checking

Function

Bits

Self-refresh

SDRFCNT0

DSFENCm, DSFEN

Initialization sequence

SDIR1

DINIRQCm, DINIRQ

Power-down

SDPWDCNT

DPWDCm, DPWD

Deep-power-down

SDDPDCNT

DDPDCm, DDPD

Mode register setting

SDmMOD

DMR

Note:

Execution of a self-refresh, a transition to or recovery from power-down or deep-power-

down mode, an initialization sequence, or mode register setting may only be performed

when all status bits are cleared to 0. Do not rewrite the registers (bits) listed below when

any of the status bits (DSRFST, DINIST, DPWDST, DDPDST, DMRSST) is set to 1.

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