SH7261 datasheet(268/1348 Pages) RENESAS

268 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 236 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

11 to 9

DPCG[2:0] Undefined

R/W

Row Precharge Interval Setting

These bits specify the minimum number of cycles that

must elapse between the SDRAM deactivation

command (PRA) and the next valid command.

000: 1 cycles

111: 8 cycles

DWR

R/W

Write Recovery Interval Setting

This bit specifies the minimum interval that must elapse

between the SDRAM write command (WRITE) and

deactivation (PRA).

0: 1 cycles

1: 2 cycles

7 to 3



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

2 to 0

DCL[2:0]

Undefined

R/W

SDRAM Controller Column Latency Setting

These bits specify the column latency of the SDRAM

controller. This setting only affects the latency setting

on the SDRAM controller side. To specify the column

latency for externally connected SDRAM it is

necessary to use the separate SDRAMm mode register

(SDmMOD), which is described below.

000: Setting prohibited

001: 1 cycles

010: 2 cycles

011: 3 cycles

1xx: Setting prohibited

[Legend]

x: Don't care

SH7261 Datasheet(PDF) 268 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 268 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL