SH7261 datasheet(265/1348 Pages) RENESAS

265 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 233 of 1312

REJ09B0320-0200

9.4.12

SDRAM Deep-Power-Down Control Register (SDDPWDCNT)

SDDPWDCNT controls transition to and recovery from deep-power-down mode.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRRRRRR

R/W

—

——

—

DDPD

Bit

Bit Name

Initial

Value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DDPD

R/W

SDRAM Common Deep-Power-Down Enable

This bit controls transition to and recovery from deep-

power-down mode for all channels simultaneously.

Setting DDPD to 1 causes all SDRAM channels to

transition to deep-power-down mode. Clearing DDPD

to 0 causes all SDRAM channels to recover from deep-

power-down mode. If an auto-refresh is in progress,

the transition to deep-power-down mode is delayed

until the auto-refresh completes.

0: Deep-power-down disabled

1: Deep-power-down enabled

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