SH7261 datasheet(267/1348 Pages) RENESAS

267 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 235 of 1312

REJ09B0320-0200

9.4.14

SDRAMm Timing Register (SDmTR) (m = 0, 1)

SDmTR specifies the timing for read and write accesses to SDRAM.

Bit:

Initial value:

R/W:

9876543210

Bit:

Initial value:

R/W:

0000000000000

—

RRRRRRRRRRRRR

R/W

——————

0000

—

R/W

RRRRR

R/W

—————————————

DWR

DRAS[2:0]

—

DRCD[1:0]

DPCG[2:0]

—

DCL[2:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 19



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

18 to 16 DRAS[2:0] Undefined

R/W

Row Active Interval Setting

These bits specify the minimum interval that must

elapse between the SDRAM row activation command

(ACT) and deactivation (PRA).

000: 1 cycle

111: 8 cycles

15, 14



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

13, 12

DRCD[1:0] Undefined

R/W

Row Column Latency Setting

These bits specify the SDRAM row column latency.

00: 1 cycles

01: 2 cycles

10: 3 cycles

11: 4 cycles

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