SH7261 datasheet(272/1348 Pages) RENESAS

272 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 240 of 1312

REJ09B0320-0200

9.4.17

SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT)

SDCKSCNT enables or disables the clock stop control signal (internal signal in the chip) and

specifies the number of assert cycles.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRR

R/W

000000000001111

R/W

—

DCK

SEN

—

————————

—

DCKSC[7:0]

Bit

Bit Name

Initial

Value

R/W

Description

31 to 17



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DCKSEN

R/W

Clock Stop Control Signal Enable

This bit is used to enable or disable the clock stop

control signal. When enabled, the clock stop control

signal operates during transition to and from deep-

power-down mode and stops the CKIO (high level).

When disabled, the clock stop control signal stays low

level.

0: Clock stop control signal disabled

1: Clock stop control signal enabled

15 to 8



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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