SH7261 datasheet(276/1348 Pages) RENESAS

276 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 244 of 1312

REJ09B0320-0200

4. Tn1 to Tnm (CS Delay Cycle)

These are the cycles between the wait end cycle and when

CSn is negated (high level). The

negation timing can be controlled using write data output delay cycles. The number of cycles is

counted beginning from the wait end cycle. In write access or if the number of CS delay cycles

during a read is other than 0 or 1, the succeeding bus access can start from the cycle following

the CS delay cycle end. If the number of CS delay cycles is 0 or 1 in read access, the

succeeding bus access can start after the end of the read data sample cycle (see below).

5. Trd (Read Data Sample Cycle)

This is the sample cycle for read data.

(2)

Page Access

Page read and write operation is employed for bus accesses for which page access can be used if

page write access enable (PWENB = 1) and page read access enable (PRENB = 1) have been

selected. Page access is used in the following cases.

1. CPU burst access (cache replacement)

2. When longword (32-bit) access to an 8-bit or 16-bit external data bus has been performed

3. When word (16-bit) access to an 8-bit external data bus has been performed

Table 9.6 shows the way addresses are modified in cases 1 above.

Table 9.6

Address Modification during Burst Access

Bus Master

Burst Mode

Address Modification

CPU

Increment

Incremented by single transfer byte count only.

Note:

Wrap boundary: Single transfer byte count × Burst transfer length

Figure 9.4 shows the basic operation of the external bus control signals in page read operation, and

figure 9.5 shows the basic operation of these signals in write operation. Note that if the number of

data bits accessed in a single burst is greater than the single page access bit boundary setting of the

PBCNT bits in the mode register, a single burst access will trigger multiple page accesses.

Regardless of whether the bust mode is increment or wraparound, page access stops temporarily

(the

CSn signal is negated) at the point when the address exceeds the page boundary, and page

access operation starts again. If the number of data bits accessed in a single burst is smaller than

the page boundary bit count, a single page access is sufficient to complete the burst transfer.

SH7261 Datasheet(PDF) 276 Page - Renesas Technology Corp