SH7261 datasheet(280/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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280 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 248 of 1312

REJ09B0320-0200

(b)

Page Access Operation

The initial data read/write operation is the same as a normal read/write operation. That is, when

the

WAIT signal is low two cycles before the end of the wait cycles (Tend), external wait cycles

are inserted. After the

WAIT signal has gone high, the wait cycles end (Tend) two cycles later.

In the second and subsequent read accesses, the page wait cycle is extended if the

WAIT signal is

low two cycles before the end of the page access wait cycle (Tend), and the page wait cycles end

two cycles after the

WAIT signal has gone high.

Figure 9.6 shows an example of external wait timing for page read access using longword (32-bit)

access to a 16-bit channel.

→

CKIO

Don't care

(Tend)

Tend

→

(Tend)

Tend

A27 to A0

CSn

WAIT

D31 to D0

Cycle wait

External

wait

Page cycle

wait

External

wait

Figure 9.6 External Wait Timing Example (Page Read Access to 16-Bit Channel)

SH7261 Datasheet(PDF) 280 Page - Renesas Technology Corp