SH7261 datasheet(282/1348 Pages) RENESAS

282 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 250 of 1312

REJ09B0320-0200

(b)

16-Bit Bus Channel

If a 16-bit bus is selected by the external bus width select bits in the CSn control register, A27 to

A1 are enabled as address signals for word units and A0 is disabled (fixed low level). Table 9.8

shows the data alignment corresponding to byte addresses for different data sizes.

Pins

WR1 and WR0 are enabled when byte strobe mode (WRMOD = 0) is selected. Pins WR3

and

WR2 are disabled. Pins BC3 to BC0 are not used.

Only the

WR1 pin is enabled when one-write strobe mode (WRMOD = 1) is selected. A low-level

signal is output from the

WR1 pin during write access, regardless of the data size. At this time the

WR0 pin is disabled (fixed high level). The valid byte positions are indicated by pins BC1 and

BC0.

Table 9.8

Data Alignment (16-Bit Bus Channel)

DATA

WR/BC

Data Size

Byte Address

(Lower 2 Bits)

[31:24]

[23:16]

[15:8]

[7:0]

[3]

[2]

[1]

[0]

Byte

Word

Longword

0 (1st)

2 (2nd)

Note:

The valid bits in the data bus for each data size are indicated by circles (O).

Crosses (

×) indicate bus data bits that are undefined.

Asterisks (*) indicate write/byte control bits that are disabled (fixed high level).

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