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SH7261 Datasheet(PDF) 285 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 285 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 253 of 1312
REJ09B0320-0200
Table 9.10
SDRAMC Commands
Command
SDCS
SDRAS
SDCAS
SDWE
SDCKE
BA1
BA0
DSL
Deselect
H
X
X
X
X
X
X
ACT
Initialize row and bank
L
L
H
H
H
V
V
RD
Read
L
H
L
H
H
V
V
WR
Write
L
H
L
L
H
V
V
PRA
Precharge all banks
L
L
H
L
H
X
X
RFA
Auto-refresh
L
L
L
H
H
X
X
MRS
Mode register set
L
L
L
L
H
L
L
EMRS
Extended mode
register set
L
L
L
L
H
H
L
RFS
Self-refresh entry
L
L
L
H
H
→ L
X
X
RFX
Self-refresh exit
H
X
X
X
L
→ H
X
X
DPD
Deep-power-down
L
H
H
L
H
→ L
X
X
DPDX
Deep-power-down exit
X
X
X
X
L
→ H
X
X
[Legend]
H: High level, L: Low level, V: Valid, X: Don't care
(3)
SDRAMC Register Setting Conditions
Rewriting of SDRAMC registers should only be performed when all of the conditions listed in
table 9.11 are satisfied.
Table 9.11
Register Rewrite Conditions
Function/Operation
Register
Conditions
Self-refresh
SDRFCNT0
• SDRAM access disabled (set in SDRAMCm*1)
• Auto-refresh enabled (DRFEN = 1)
• Power-down disabled (DPWD/DPWDCI = 0)
• Deep-power-down disabled (DDPD/DDPDCI = 0)
Auto-refresh
SDRFCNT1
• Self-refresh disabled (DSFEN/DSFENCI = 0)
• Power-down disabled (DPWD/DPWDCI = 0)
SDIR0
• Before start of initialization sequence
Initialization sequence
SDIR1
• After reset or after recovery from deep-power-
down



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