SH7261 datasheet(289/1348 Pages) RENESAS

289 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 257 of 1312

REJ09B0320-0200

(6)

Initialization Sequencer

SDRAMC is provided with a sequencer for issuing the commands for SDRAM initialization. The

initialization sequence should always be initiated a single time only following a reset (all

channels) and following recovery from deep-power-down mode (individual channels). In such

cases operation cannot be guaranteed if the initialization sequence is not performed, or if it is

performed more than once.

The SDRAM initialization sequence issues the precharge-all-banks command followed by n (n = 1

to 15) auto-refresh commands, in that order. Make timing settings for the initialization sequencer

to SDRAM initialization register 0 (SDIR0). Initialization sequences are initiated using SDRAM

initialization register 1 (SDIR1).

Note that an initialization sequence for all channels is initiated using the DINIRQ bit.

Figure 9.10 shows a timing example for the initialization sequence. Setting DARFC to specify two

or more times causes multiple initialization auto-refresh cycles to be performed.

CKIO

DSL: Deselect command

RFA: Auto-refresh command

PRA: Precharge-all-banks command

SDRAM command

Initialization precharge cycle

Initialization auto-refresh cycle

DINST bit value

changes to 0

PRA

DSL

DPC

DARFI

DSL

RFA

DSL

Figure 9.10 Initialization Sequence Timing Example

(DPC Bit Set Value: 001, DARFI Bit Set Value: 0001, DARFC Bit Set Value: 001)

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