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SH7261 Datasheet(PDF) 291 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 291 Page - Renesas Technology Corp |
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291 / 1348 page ![]() Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 259 of 1312 REJ09B0320-0200 (8) Deep-Power-Down Mode SDRAMC supports an SDRAM deep-power-down mode. In deep-power-down mode SDRAMC issues a deep-power-down command and drives the SDCKE signal low level. Transition to and recovery from deep-power-down mode are performed using the SDRAM deep- power-down control register (SDDPDCNT). Setting the DDPD bit to 1 causes SDRAMC to put all channels into deep-power-down mode. Clearing the DDPD bit to 0 causes SDRAMC to recover from deep-power-down mode. During recovery from deep-power-down mode, SDRAMC issues a deep-power-down exit command and drives the SDCKE signal high level. Following recovery from deep-power-down exit, wait for the duration designated for the SDRAM being used and then execute an initialization sequence. CKIO SDCKE SDRAM command SDRAMC deep-power-down mode Deep-power-down command DPD Deep-power-down exit command DPDX Figure 9.13 SDRAMC Deep-Power-Down Mode |
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