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SH7261 Datasheet(PDF) 294 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 294 Page - Renesas Technology Corp |
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294 / 1348 page ![]() Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 262 of 1312 REJ09B0320-0200 CKIO ACT: Row and bank activation command WR: Write command PRA: Precharge-all command DSL: Deselect command SDRAM command Data bus Multiple write ACT WR DSL WR DSL WR DSL WR PRA d1 d2 d3 d0 Figure 9.17 Multiple Write Timing Example (Multiple Write of 4 Data Units, Shortest Timing Settings) Non-Consecutive Write Commands Issued CKIO ACT: Row and bank activation command WR: Write command PRA: Precharge-all command SDRAM command Data bus Multiple write Row address A Row address B ACT WR WR WR PRA ACT WR PRA d0 d1 d2 d3 Figure 9.18 Multiple Write Timing Example (Multiple Write of 4 Data Units, Shortest Timing Settings) Access Spanning Rows |
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