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SH7261 Datasheet(PDF) 298 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 298 Page - Renesas Technology Corp |
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298 / 1348 page ![]() Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 266 of 1312 REJ09B0320-0200 Figures 9.24 and 9.25 show the operation timing of the clock stop control signal. Deep-power-down mode DDPDST bit value changes to 0 CKIO CLKSTOP (internal signal) SDCKE DCKSC DPD SDRAM command DPD: Deep-power-down entry command Figure 9.24 Clock Stop Control Signal Operation Timing (Transition to Deep-Power-Down Mode) Deep-power-down mode DDPD bit cleared to 0 DDPDST bit value changes to 1 DDPDST bit value changes to 0 CKIO CLKSTOP (internal signal) SDCKE DCKSC DPDX SDRAM command DPDX: Deep-power-down exit command Figure 9.25 Clock Stop Control Signal Operation Timing (Recovery from Deep-Power-Down Mode) |
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