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SH7261 Datasheet(PDF) 296 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 296 Page - Renesas Technology Corp |
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296 / 1348 page  Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 264 of 1312 REJ09B0320-0200 (c) Byte Access Control by DQM Figures 9.21 and 9.22 show timing examples for byte accesses to the SDRAM with a 16-bit bus width. In the SDRAM access, the DQM signal is asserted when data is masked. CKIO DQM1 DQM0 Low level Data bus [7:0] Data bus [15:8] High-Z ACT WR PRA d0 SDRAM command Figure 9.21 Byte Write Timing to SDRAM with 16-Bit Bus Width (Example) CKIO DQM1 DQM0 Data bus [7:0] Data bus [15:8] High-Z ACT RD DSL PRA d0 SDRAM command Low level Figure 9.22 Byte Read Timing from SDRAM with 16-Bit Bus Width (Example) |
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