SH7261 datasheet(297/1348 Pages) RENESAS

297 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 265 of 1312

REJ09B0320-0200

(10) Mode Register Setting

Writing to the SDRAMm mode register (SDmMOD) causes mode register set commands and

extended mode register set commands to be issued to the various channels. Settings to the

SDRAMm mode register (SDmMOD) should be made individually for each channel.

Figure 9.23 shows the operation timing for mode register setting.

CKIO

DSL:

Deselect command

MRS:

Mode register set command

EMRS: Extended mode register set command

SDRAM command

Mode register

setting cycle

Extended mode register

setting cycle

MRS

DSL

EMRS

DSL

3 cycles (fixed)

Figure 9.23 Operation Timing for Mode Register Setting

(11) Clock Stop Control Signal

SDRAMC outputs a clock stop control signal (CLKSTOP). CLKSTOP can be enabled or disabled

using the DCKSEN bit in the SDRAM clock stop control signal setting register (SDCKSCNT).

The CLKSTOP signal remains low level when the clock stop control signal is disabled.

When clock stop control signal is enabled, the CLKSTOP and CKIO signals operate in

conjunction with transition to and recovery from deep-power-down mode.

During a transition to deep-power-down mode, the CLKSTOP signal goes high after the deep-

power-down entry command is issued. During a recovery from deep-power-down mode, the

CLKSTOP signal goes low and a deep-power-down exit command is issued when the clearing of

the DDPD bit to 0 is accepted by SDRAMC and the CKIO starts operation.

DCKSC, the period between the change of CLKSTOP along with CKIO and the issuance of deep

power-down entry or exit command, can be set by the SDRAM clock stop control signal setting

SH7261 Datasheet(PDF) 297 Page - Renesas Technology Corp