SH7261 datasheet(290/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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290 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 258 of 1312

REJ09B0320-0200

(7)

Power-Down Mode

SDRAMC supports an SDRAM power-down mode. In power-down mode the SDCKE signal from

SDRAMC goes low level. While in power-down mode auto-refresh operations are performed at

the interval specified by the auto-refresh request interval setting (DRFC) bits in SDRAM refresh

control register 1 (SDRFCNT1). The SDCKE signal only goes high when an auto-refresh

command is issued.

Transition to and recovery from power-down mode are performed using the SDRAM power-down

control register (SDPWDCNT).

Setting the DPWD bit to 1 causes SDRAMC to transition to power-down mode. Clearing the

DPWD bit to 0 causes SDRAMC to recover from power-down mode.

The SDCKE signal from SDRAMC goes high level when recovery from power-down mode

occurs.

CKIO

SDCKE

SDRAMC power-down mode

Figure 9.11 SDRAMC Power-Down Mode

CKIO

SDCKE

SDRAM command

SDRAMC power-down mode

Auto-refresh command

RFA

Figure 9.12 Auto-Refresh Operation in SDRAMC Power-Down Mode

SH7261 Datasheet(PDF) 290 Page - Renesas Technology Corp