SH7261 datasheet(286/1348 Pages) RENESAS

286 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 254 of 1312

REJ09B0320-0200

Function/Operation

Conditions

Power-down

SDPWDCNT

• SDRAM access disabled (set in SDRAMCm*1)

• Auto-refresh enabled (DRFEN = 1)

• Self-refresh disabled (DSFEN/DSFENCI = 0)

• Deep-power-down disabled (DDPD/DDPDCI = 0)

Deep-power-down

SDDPDCNT

• SDRAM access disabled (set in SDRAMCm*1)

• Self-refresh disabled (DSFEN/DSFENCI = 0)

• Auto-refresh disabled (DRFEN = 0)

• Power-down disabled (DPWD/DPWDCI = 0)

Address register settings

SD0ADR,

SD1ADR

• Auto-refresh disabled (DRFEN = 0)

• SDRAM access disabled (set in SDRAMCm*1)

• Self-refresh disabled (DSFEN/DSFENCI = 0)

• Power-down disabled (DPWD/DPWDCI = 0)

• Deep-power-down disabled (DDPD/DDPDCI = 0)

Timing register settings

SD0TR,

SD1TR

• Self-refresh in progress (DSFEN/DSFENCI = 1)

• Self-refresh disabled (DSFEN/DSFENCI = 0)

• Auto-refresh disabled (DRFEN = 0)

• SDRAM access disabled (set in SDRAMCm*1)

Mode register settings

SD0MOD,

SD1MOD*

• SDRAM access disabled (set in SDRAMCm*1)

• Self-refresh disabled (DSFEN/DSFENCI = 0)

• Power-down disabled (DPWD/DPWDCI = 0)

• Deep-power-down disabled (DDPD/DDPDCI = 0)

Clock stop control signal

settings

SDCKSCNT

• Deep-power-down disabled (DDPD/DDPDCI = 0)

Notes: 1. After writing 0 to EXENB, check to confirm that the EXENB bit has been cleared to 0.

2. Do not fail to confirm that all status bits in the SDRAM status register (SDSTR) have

been cleared to 0 before rewriting this bit.

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