SH7261 datasheet(258/1348 Pages) RENESAS

258 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 226 of 1312

REJ09B0320-0200

9.4.7

SDRAM Refresh Control Register 0 (SDRFCNT0)

SDRFCNT0 controls self-refresh operation.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

RRRRRRRRRRRRRRRR

0000000000000000

RRRRRRRRRRRRRRR

R/W

—

——

—

DSFEN

Bit

Bit Name

Initial

Value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

DSFEN

R/W

SDRAM Common Self-Refresh Operation Enable

This bit controls self-refresh operation for all channels

simultaneously. Setting DSFEN to 1 performs auto-

refresh cycle operation, immediately after which self-

refresh operation begins. Clearing DSFEN to 0 ends

self-refresh operation, and auto-refresh operation

resumes immediately afterward. The value written to

this bit is reflected when self-refresh operation starts, if

DSFEN was set to 1, or when auto-refresh operation

starts following the end of self-refresh operation, if

DSFEN was cleared to 0.

0: Self-refresh disabled

1: Self-refresh enabled

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