SH7261 datasheet(250/1348 Pages) RENESAS

250 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 218 of 1312

REJ09B0320-0200

To disable the operation for each channel, forcibly write out data tentatively stored in internal

write buffer. The procedure is as follows:

1. Execute read access to the channel whose operation is to be disabled.

2. Then, write 0 to the EXENB bit (operation disabled).

9.4.4

CSn Mode Register (CSMODn) (n = 0 to 6)

CSMODn selects the mode for page read access and the bit boundary for page access, enables

page read/write access and external wait, and selects the mode for write access.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

0000000000000000

R/W

0000000000000000

RRRRRRRRRRRRRRRR

MOD

—

PBCNT[1:0]

—

ENB

————

ENB

——

MOD

————————————————

Bit

Bit Name

Initial

Value

R/W

Description

PRMOD

R/W

Page Read Access Mode Select

This bit selects the operating mode for page read

access. Clearing PRMOD to 0 selects the normal

access compatible mode. In this mode the

RD signal is

negated each time a unit of data is read and an RD

assert wait is inserted. Setting PRMOD to 1 selects the

external data read sequential assert mode. In this

mode

RD is asserted continuously between page

accesses.

0: Normal access compatible mode

1: External data read sequential assert mode



Reserved

This bit is always read as 0. The write value should

always be 0.

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