SH7261 datasheet(248/1348 Pages) RENESAS

248 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 216 of 1312

REJ09B0320-0200

Bit

Bit Name

Initial

Value

R/W

Description

19 to 16 RRCV[3:0]

0000

R/W

Post-Read Data Recovery Cycle Setting

These bits specify the number of data recovery cycles

to be inserted after read accesses to the external bus.

If a value other than 0 is selected, data recovery cycles

are inserted in the following cases:

If a read access to the external bus is followed by a

write access to the external bus. (Data recovery cycles

are inserted even when access is performed

sequentially to the same CSC channel.)

If a read access to the external bus is followed by a

read access to a different CSC channel. (No data

recovery cycles are inserted in cases of sequential

read accesses to the same CSC channel.)

Note that if idle cycles occur between accesses to the

external bus, the number of data recovery cycles

inserted is reduced by the number of idle cycles.

0000: 0 cycle

0001: 1 cycles

1111: 15 cycles

15 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

Notes: 1. When accessing SDRAM, there is no danger of data collision on the bus due to timing.

Consequently, there is no data recovery cycle setting for SDRAM. (The value is fixed at

0 cycles.)

2. Writing to the CSn recovery cycle setting register (CSnREC) must be done while CSC

for the corresponding channel is disabled (EXENB

= 0). Only channel 0 (CS0) can be

enabled by setting EXENB = 1. To enable channel 0, stop the DMAC and set EXENB to

1 between the reset release and data write access to CS0.

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