SH7261 datasheet(243/1348 Pages) RENESAS

243 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 211 of 1312

REJ09B0320-0200

9.4

The BSC has the following registers.

All registers are initialized by a power-on reset or in deep standby mode.

Do not access spaces other than area 0 until settings are completed for the connected memory

interface.

Table 9.4

Abbreviation

R/W

Initial Value

Address

Access

Size

CS0 control register

CS0CNT

R/W

H'00010000/

H'00110000/

H'00210000*

H'FF420000

8, 16, 32

CS0 recovery cycle setting

CS0REC

R/W

H'00000000

H'FF420008

8, 16, 32

CS1 control register

CS1CNT

R/W

H'00000000

H'FF420010

8, 16, 32

CS1 recovery cycle setting

CS1REC

R/W

H'00000000

H'FF420018

8, 16, 32

CS2 control register

CS2CNT

R/W

H'00000000

H'FF420020

8, 16, 32

CS2 recovery cycle setting

CS2REC

R/W

H'00000000

H'FF420028

8, 16, 32

CS3 control register

CS3CNT

R/W

H'00000000

H'FF420030

8, 16, 32

CS3 recovery cycle setting

CS3REC

R/W

H'00000000

H'FF420038

8, 16, 32

CS4 control register

CS4CNT

R/W

H'00000000

H'FF420040

8, 16, 32

CS4 recovery cycle setting

CS4REC

R/W

H'00000000

H'FF420048

8, 16, 32

CS5 control register

CS5CNT

R/W

H'00000000

H'FF420050

8, 16, 32

CS5 recovery cycle setting

CS5REC

R/W

H'00000000

H'FF420058

8, 16, 32

CS6 control register

CS6CNT

R/W

H'00000000

H'FF420060

8, 16, 32

CS6 recovery cycle setting

CS6REC

R/W

H'00000000

H'FF420068

8, 16, 32

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