SH7261 datasheet(230/1348 Pages) RENESAS

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Section 8 Cache

Rev. 2.00 Sep. 07, 2007 Page 198 of 1312

REJ09B0320-0200

(2)

Write Miss

In write-back mode, an external bus cycle starts when a write miss occurs, and the entry is

updated. The way to be replaced follows table 8.4. When the U bit of the entry to be replaced is 1,

the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written

to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way

becomes the latest. After the cache completes its update cycle, the write-back buffer writes the

entry back to the memory. The write-back unit is 16 bytes.

In write-through mode, no write to cache occurs in a write miss; the write is only to the external

memory.

8.3.5

Write-Back Buffer (Only for Operand Cache)

When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to

the external memory. To increase performance, the entry to be replaced is first transferred to the

write-back buffer and fetching of new entries to the cache takes priority over writing back to the

external memory. After the cache completes to fetch the new entry, the write-back buffer writes

the entry back to external memory. During the write-back cycles, the cache can be accessed. The

write-back buffer can hold one line of cache data (16 bytes) and its physical address. Figure 8.3

shows the configuration of the write-back buffer.

Longword 0

Longword 1

Longword 2

Longword 3

A (31 to 4)

A (31 to 4):

Physical address written to external memory (upper three bits are 0)

Longword 0 to 3: One line of cache data to be written to external memory

Figure 8.3 Write-Back Buffer Configuration

Operations in sections 8.3.2 to 8.3.5 are compiled in table 8.8

SH7261 Datasheet(PDF) 230 Page - Renesas Technology Corp