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SH7261 Datasheet(PDF) 313 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 313 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 281 of 1312
REJ09B0320-0200
Table 9.17
Case for 8-Bit External Data Bus Width (BSIZE*
1
= (1, 0))
SDRAM
Type
Number
64 Mbits (
×8)
1
128 Mbits (
×8)
1
256 Mbits (
×8)
1
512 Mbits (
×8)
1
DSZ*
2
001 (8 Mbytes)
010 (16 Mbytes)
011 (32 Mbytes)
100 (64 Mbytes)
DDBW*
3
00 (8 bits)
00 (8 bits)
00 (8 bits)
00 (8 bits)
This LSI
address
Row
Address
Column
Address
Row
Address
Column
Address
Row
Address
Column
Address
Row
Address
Column
Address
A16 (/BA1)*
4
addr22*
5
addr22*
5
addr23*
5
addr23*
5
addr24*
5
addr24*
5
addr25*
5
addr25*
5
A15 (/BA0)*
4
addr21*
5
addr21*
5
addr22*
5
addr22*
5
addr23*
5
addr23*
5
addr24*
5
addr24*
5
A14 (/MA12)*
4
L
L
L
L
addr22*
5
L
addr23*
5
L
A13 (/MA11)*
4
addr20*
5
L
addr21*
5
L
addr21*
5
L
addr22*
5
addr10*
5
A12 (/MA10)*
4
addr19*
5
*
6
addr20*
5
*
6
addr20*
5
*
6
addr21*
5
*
6
A11 (/MA9)*
4
addr18*
5
L
addr19*
5
addr9*
5
addr19*
5
addr9*
5
addr20*
5
addr9*
5
A10 (/MA8)*
4
addr17*
5
addr8*
5
addr18*
5
addr8*
5
addr18*
5
addr8*
5
addr19*
5
addr8*
5
A9 (/MA7)*
4
addr16*
5
addr7*
5
addr17*
5
addr7*
5
addr17*
5
addr7*
5
addr18*
5
addr7*
5
A8 (/MA6)*
4
addr15*
5
addr6*
5
addr16*
5
addr6*
5
add16*
5
addr6*
5
addr17*
5
addr6*
5
A7 (/MA5)*
4
addr14*
5
addr5*
5
addr15*
5
addr5*
5
addr15*
5
addr5*
5
addr16*
5
addr5*
5
A6 (/MA4)*
4
addr13*
5
addr4*
5
addr14*
5
addr4*
5
addr14*
5
addr4*
5
addr15*
5
addr4*
5
A5 (/MA3)*
4
addr12*
5
addr3*
5
addr13*
5
addr3*
5
addr13*
5
addr3*
5
addr14*
5
addr3*
5
A4 (/MA2)*
4
addr11*
5
addr2*
5
addr12*
5
addr2*
5
addr12*
5
addr2*
5
addr13*
5
addr2*
5
A3 (/MA1)*
4
addr10*
5
addr1*
5
addr11*
5
addr1*
5
addr11*
5
addr1*
5
addr12*
5
addr1*
5
A2 (/MA0)*
4
addr9*
5
addr0*
5
addr10*
5
addr0*
5
addr10*
5
addr0*
5
addr11*
5
addr0*
5
Notes: 1. The legend BSIZE represents the BSIZE bit in the SDRAMCm control register.
2. The legend DSZ represents the DSZ bit in the SDRAMm address register.
3. The legend DDBW represents the DDBW bit in the SDRAMm address register.
4. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and
SDRAM address respectively.
5. Addresses addr25 to addr0 are the logical addresses used by the CPU and DMAC in
access to the SDRAM.
6. When the RD, WR or PRA command is issued, this carries the pre-charge option
signal.



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