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SH7261 Datasheet(PDF) 312 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 312 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 280 of 1312
REJ09B0320-0200
(13) External Address/SDRAM Address Signal Multiplex
(a)
Address Multiplex
Either of addresses used for accessing external device or SDRAM is output through external
address pins. The SDRAM address is shifted internally by changing the settings of DDBW and
DSZ in SDmADR and BSIZE in SDCmCNT. The bank address is output on A16 and A15 and the
address is output on A14 to A2.
Table 9.16
External Address/SDRAM Address Pins
Pin Name
Function
Pin Name
Function
A27
External address
A13 (/MA11) External address/SDRAM address
A26
External address
A12 (/MA10) External address/SDRAM address
A25
External address
A11 (/MA9)
External address/SDRAM address
A24
External address
A10 (/MA8)
External address/SDRAM address
A23
External address
A9 (/MA7)
External address/SDRAM address
A22
External address
A8 (/MA6)
External address/SDRAM address
A21
External address
A7 (/MA5)
External address/SDRAM address
A20
External address
A6 (/MA4)
External address/SDRAM address
A19
External address
A5 (/MA3)
External address/SDRAM address
A18
External address
A4 (/MA2)
External address/SDRAM address
A17
External address
A3 (/MA1)
External address/SDRAM address
A16 (/BA1)
External address/SDRAM bank address
A2 (/MA0)
External address/SDRAM address
A15 (/BA0)
External address/SDRAM bank address
A1
External address
A14 (/MA12) External address/SDRAM address
A0
External address
(b)
Address Register Setting Value and Supported SDRAM Configuration
Tables 9.17 to 9.19 are the SDRAM configurations that to support for 8-, 16-, or 32-bit bus width.
These tables are featured to ease the understanding of the relationships between the SDRAM to
support and address multiplex.
Addresses addr27 to addr0 are the logical addresses used by the CPU and DMAC in access to the
SDRAM. The table below shows how the settings of DSZ and DDBW determine which signals
are output on the SDRAM-access pins.



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