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SH7261 Datasheet(PDF) 309 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 309 Page - Renesas Technology Corp |
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309 / 1348 page ![]() Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 277 of 1312 REJ09B0320-0200 CKIO ACT: Row and bank activation command RD: Read command DSL: Deselect command PRA: Precharge-all command SDRAM command Data bus Single read Note: If the interval set in DRAS ends before RD, PRA is issued in the table size after RD. ACT DSL RD PRA DSL DRCD (ACT-RD) DRAS (ACT-PRA) DCL (RD-d) DPCG (PRA-next) d Figure 9.37 Single Read Timing Example 2 CKIO ACT: Row and bank activation command RD: Read command PRA: Precharge-all command SDRAM command Data bus Single read ACT DSL RD PRA DSL DRCD (ACT-RD) DRAS (ACT-PRA) DCL (RD-d) DPCG (PRA-next) d Figure 9.38 Single Read Timing Example 3 |
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