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SH7261 Datasheet(PDF) 306 Page - Renesas Technology Corp |
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SH7261 Datasheet(HTML) 306 Page - Renesas Technology Corp |
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306 / 1348 page  Section 9 Bus State Controller (BSC) Rev. 2.00 Sep. 07, 2007 Page 274 of 1312 REJ09B0320-0200 • Multiple Write Timing Setting Examples Figures 9.33 to 9.35 show the correspondence between the timing of multiple write operations involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table 9.13 shows the SDRAMm timing register (SDmTR) set values for each figure. Table 9.13 SDITR Set Value Correspondence Table (Multiple Write Timing) Figure DRAS DRCD DPCG DWR Figure 9.33 010 00 001 0 Figure 9.34 000 01 001 0 Figure 9.35 000 01 001 1 CKIO ACT: Row and bank activation command WR: Write command PRA: Precharge-all command SDRAM command Data bus Multiple write ACT WR WR WR WR PRA DSL d0 DRCD (ACT-WR) DRAS (ACT-PRA) DWR (WR-PRA) DPCG (PRA-next) d1 d2 d3 Figure 9.33 Multiple Write Timing Example 1 |
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