SH7261 datasheet(303/1348 Pages) RENESAS

303 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 271 of 1312

REJ09B0320-0200

Figure 9.29 shows the procedure for recovering from deep-power-down mode.

Deep-power-down mode

Access enabled status

(EXENB = 1)

End deep-power-down mode

(1) Confirm that all status bits in SDSTR have been cleared to 0

(2) Clear deep-power-down enable bit to 0 by means of program assigned to

other than to corresponding channel area

Standby

Use a timer, etc., to wait for the same duration as the standby time specified

in the power-on sequence (determined by specifications of SDRAM used)

Initialization sequence

(1) Set initialization sequence start bit (DINIRQm) to 1 by means of program

assigned to other than to corresponding channel area

(2) Wait for initialization sequence start bit (DINISTm) to be cleared to 0

Mode register setting

(1) Perform mode register setting

(2) Perform extended mode register setting

Start auto-refresh

Set DRFEN bit in SDRFCNT1 to 1

Figure 9.29 Procedure for Recovery from Deep-Power-Down Mode

Note:

Before transitioning to or recovering from deep-power-down mode it is necessary to halt

SDRAM access to the affected channels. Consequently, it is not possible to transition to or

recover from deep-power-down mode while programs or DMA operations that access

SDRAM are in progress. Pay attention to the following points when writing programs.

• Before transitioning to deep-power-down mode, halt any DMA channel transfers that

access the SDRAM area of the affected channels.

• Make sure that programs run while transitioning to deep-power-down mode, while in

deep-power-down mode, or while recovering from deep-power-down mode do not

access operands or fetch (or pre-fetch) instructions stored in the SDRAM area.

SH7261 Datasheet(PDF) 303 Page - Renesas Technology Corp