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SH7261 Datasheet(PDF) 308 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 308 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 2.00 Sep. 07, 2007 Page 276 of 1312
REJ09B0320-0200
• Single Read Timing Setting Examples
Figures 9.36 to 9.38 show the correspondence between the timing of single read operations and
the set values of the SDRAMm timing register (SDmTR). Table 9.14 shows the SDRAMm
timing register (SDmTR) set values for each figure.
Table 9.14
SDITR Set Value Correspondence Table (Single Read Timing)
Figure
DRAS
DRCD
DPCG
DCL
Figure 9.36
010
00
001
010
Figure 9.37
000
01
001
010
Figure 9.38
000
01
001
011
CKIO
ACT: Row and bank activation command
RD:
Read command
PRA: Precharge-all command
SDRAM command
Data bus
Single read
ACT
RD
DSL
PRA
DSL
DRCD
(ACT-RD)
DRAS
(ACT-PRA)
DCL
(RD-d)
DPCG
(PRA-next)
d
Figure 9.36 Single Read Timing Example 1



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